In response to trends in current technological developments , not only SoC chip designs are more complex, but also chip performance and low power requirements are critical, forcing IC designers to face more challenges. The track invite Taiwan and foreign AMS designers to share their design experience and collaboration experience with Synopsys solutions. You will see excellent sharing on custom design(Custom Compiler and Laker), circuit simulation(HSPICE, FineSim, and CustomSim), and characterization(Silicon Smart). You will also see the latest updates for Synopsys AMS tools.
- Faraday Introduction
- Why Faraday Adopt Custom Compiler LE in FinFET
- Layout Environment Customization/Migration Overview
- Custom Compiler Benefit Features Sharing
Also easy define criterial rule for window DRC check and reduce layout communicate with RnD by writing some constraint in design.
For digital block routing, also provide solution to placement and routing STD cell in Laker environment. Also help some small digital block quick routing.
Laker L3+ not only improve layout productivity and also robust our design.