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SNUG TW 2021 – A Virtual Experience  


鑑於近期COVID-19疫情升溫，考量與會貴賓健康安全及配合政府強化防疫政策，SNUG Taiwan 2021 將採線上形式舉辦。誠摯邀請您一同參加SNUG Taiwan 2021線上研討會，瞭解當前IC設計及半導體產業最先進的技術和研發趨勢，以因應設計和驗證面臨的嚴峻挑戰，進而掌握產業新契機。

The health and safety of the SNUG ecosystem – including users, partners and our employees – are a top priority of Synopsys. 

Concerning the recent island-wide COVID-19 epidemic outbreaks, SNUG Taiwan Operation Team had made a decision to host SNUG Taiwan on-line. You are sincerely invited to participate in the SNUG Taiwan 2021 online seminar to learn about the most advanced technology and R&D trends of current IC design and semiconductor industry. 

About SNUG Taiwan 


SNUG Taiwan(Synopsys Users Group - Taiwan)為台灣半導體設計與製造業界規模最大的技術會議之一。因應5G、物聯網、車用電子及人工智慧(AI)等當前科技發展的重要趨勢，新思科技 (Synopsys) 在這一年一度的技術研討會中，邀請來自業界夥伴分享產品開發所面臨的挑戰，以及晶片設計與軟硬體整合新技術與解決方案。

請點選 Sign up/Login 完成預先線上報名及帳號啟用手續，即能在研討會活動期間(7/21~8/4)，隨選影片點閱觀看，並有機會獲得活動好禮。


SNUG Taiwan所有內容將於活動結束後90天上傳至新思科技技術支援服務平台SolvNetPlus。歡迎點閱SolvNetPlus影片觀看平台介紹，提前熟悉SolvNetPlus使用介面並即早登錄，以取得更多新思科技訓練課程及產品介紹相關資訊。


活動好禮：

*SNUG Taiwan 2021 活動好禮中獎名單出爈，請中獎者留意系統寄出的通知信。有任何疑問，請來信與我們聯絡。謝謝！

SNUG Taiwan 2021 活動好禮中獎名單.pdf

SolvNetPlus特別獎：活動期間完成觀看SolvNetPlus影片並填寫問卷，就有機會參加抽獎，獎品包括Apple HomePod Mini乙只(3名)，以及AirTag乙只(20名)。

參加獎：活動期間完成觀看4支(不含SolvNetPlus)影片及對應session問卷，即可獲得65W GaN氮化鎵智慧三孔電源供應器乙只。

問卷抽獎：活動期間完成觀看6支(不含SolvNetPlus)影片及對應session 問卷，並完成post-event 問卷，就有機會參加抽獎，獎品包括任天堂Switch健身組乙組(或等值獎品)，以及遊戲專用藍牙耳機麥克風乙只(或等值獎品)。

防疫期間，鼓勵參與，再新增限量加碼禮：

  • 符合前述問卷抽獎資格的參與者，可再抽300元foodpanda即享券(限量100名)
  • 符合前述問卷抽獎資格的參與者，且觀看達10支(不含SolvNetPlus)影片並完成對應session問卷，可抽500元foodpanda即享券(限量 50名)

Since 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovation from Silicon to Software. SNUG Taiwan continues to foster the link between users and technical experts so they can share best practices for electronic design and verification challenges. Join your fellow engineers at SNUG to hear practical information you can use for your current projects and the inspiration to create Smart Everything.


Please click Sign up/Login to complete the online registration and account activation. The pre-recorded presentation videos will be available on-demand starting from July 21. All content will be moved to SolvNetPlus after 90 days.

The giveaways and lucky draw incentives for SNUG Taiwan 2021 only apply to event participants in Taiwan. These prizes won’t be sent to regions or countries outside Taiwan.


備註 1：參加獎數量有限，送完為止。
備註 2：抽獎活動將線下進行，主辦單位將另行通知獲獎者；得獎名單會於抽獎結束後於活動首頁公告。
備註 3：活動僅限於台灣地區舉辦，獎品恕無法寄送至非台灣地區。
備註 4：台灣新思科技保留修改本活動規則之權利，並對活動規則擁有最終解釋權。
All rights reserved to Synopsys for agenda and gamification rules change.

Primary Agenda Introduction


主題演講：由新思科技董事長暨共同執行長Dr. Aart de Geus擔任Synopsys主題演講，並特別邀請到鴻海科技S次半導體事業群陳偉銘副總經理進行專家主題演講，分享半導體研發及先進設計新趨勢。

焦點話題：聚焦當前半導體創新應用，邀請客戶代表針對AI、車用電子以及記憶體等技術發表設計研究心得。議程主題含括：AI、Automotive、Memory、Digital Design、Custom-AMS Design、Signoff、Low Power Design & Test以及Efficient Verification等。

This year, SNUG Taiwan features insightful keynotes from industry leaders and diverse technical tracks driven by innovative user content, and leading-edge Synopsys tutorials that will provide a unique opportunity for users to attend this exciting event.


備註：往下滑動或點選上方Agenda選單，以查看詳細議程介紹。新思科技保留議程調整權。

NOTE: Pleas scroll down or click on Agenda for more detail about SNUG TW 2021 agenda. The agenda is subject to change without prior notice.

Synopsys Keynote: Welcome to the Era of SysMoore

Aart de Geus
Chairman and co-CEO, Synopsys

Even for an industry hardened against systemic and scale complexity, building a world with 1000X more compute by the end of the decade will require revolutionary approaches to architecture, groundbreaking autonomous design systems, and disruptive engineering from cloud to edge. Founder and co-CEO Aart de Geus is set to lift the veil on a highly anticipated portfolio of design instruments that will ignite an era of exponential opportunity for humankind, and shine as a beacon of the Synopsys “Yes, if…” spirit of limitless possibility.

Industry Keynote: Increase Taiwan’s semiconductor influence through creating an EV platform

Bob Wei-Ming Chen
VP of Hon Hai Technology
Head of Semiconductor Business Group


Taiwan is a giant in semiconductor industry however the market share in automotive IC is not high. Part of the reasons is because the automotive industry is very conservative and forms a close system to the outside world. EV is a new industry with sizable TAM and attractive CAGR. The use of advanced semiconductor is increasing. It is a new market that is worth Taiwan’s semiconductor companies to explore. MIH is an independent platform founded by Hon Hai to resolve the high development cost, long development time, insufficient resource in current EV development. It can help semiconductor players to access the modularized design information at the very beginning. This presentation discusses Hon Hai’s endeavors in EV semiconductor including founding the MIH platform and make it independent. Hon Hai’s semiconductor deployment and services to semiconductor companies will also be presented.

Technical Committee Paper Award

Committee Introduction
Congratulations to Our Best Paper Winners
Listen to the committee review result and learn more about paper award winners this year.
Best Paper Award
(中文簡報) PT Power ECO Machine Learning – Effective Training Data Selection
Meng Hsiu Tsai
GUC
PT power ECO machine learning can reduce the run time effectively based on high coverage training data. How to select the effective training data is important for machine learning. More training data can achieve higher coverage but induce long run time to load training data. This paper will compare the TAT/QoR for various training data selection scenarios (by different timing closure stage). Finally, an effective training data selection methodology will be summarized.
Best Paper Award
(中文簡報) Speed Up Simulation Regression TAT Using AI/ML
HH Tseng
Realtek
Verification continues to be one of the top contributors of compute costs for any chip design. Increase in design complexity also increases verification complexity and in turn the cost, hence we need solutions targeted to improve verification efficiency. There is huge value to the user in tuning the simulation environment for optimal performance since HDL simulation contributes significantly to the compute cost. The process of simulator performance tuning today is manual, depends on design/verification environment being simulated and needs expert knowledge of simulator. In this session we present DPO, an AI/ML based VCS simulator performance optimizer that targets simulation TAT reduction. It is a mostly automated system that analyzes the simulation environment, identifies and optimizes performance bottlenecks. We present the practical process, methodology and results of deployment of DPO in a production environment. DPO overcomes the above listed challenges of simulator performance tuning and contributes positively to verification efficiency by reducing the compute cost for HDL simulations.
Best Paper Award
(中文簡報) Productivity Improvement with ICCII Freeform Macro Placement
DS Fu
GUC
Floorplan is the key to good P&R QoR. It usually costs lots of iterations to analyze and finetune macro location to meet design's PPA spec. ICC2 FreeForm Placer is a new generation of engine that considers macro and STD cell's location together. It provides good QoR result compared to manual floorplan while reducing the total turnaround time of Floorplan exploration. In this presentation we show GUC's real case using ICCII FreeForm Macro Placement to tapeout. And provide some experience sharing and enhancement discussion about ICCII FreeForm Placement.
Outstanding Paper
(中文簡報) Ultimate R2N PPA Consolidation by FusionCompiler UPS Flow
Will Lin, Yuuka Huang
MediaTek Inc.
Performance/Power/Area consolidation is a legacy challenge to digital IC design flow. Take two cases as example. Case1: at synthesis stage, over-constraint is a common solution to secure PPA quality till place-and-route stage. However, Over-constraint can also lead pessimistic PPA result. Case2: traditional synthesis flow can't consider clock tree synthesis. This kind of situation can make a natural gap between synthesis and physical design as well and get a optimistic PPA result at synthesis stage. Above examples can introduce PPA un-stable through whole implementation flow. In this work, we will demonstrate how FusionCompiler UPS flow consolidate PPA in decent range from synthesis to post-route.
Outstanding Paper
(中文簡報) New Enhancements of PowerReplay from User Feedbacks
Kuma Tu
MediaTek Inc.
When the semiconductor technology advances to nanometers, designers aggressively integrate more functions into a very small die area than that with the old technology. In addition, designers also push the design speed to the limit to fulfill the performance requirement of the 3D game and AI computing, etc. Hence, this results in very high power density, and the power consumption, IR, thermal, and System PI all become much worse than before. To predict those impact correctly and efficiently, we adopt the PowerReplay to achieve similar power and IR accuracy with the post-layout simulation but much better runtime than the post-simulation. Recently, we closely collaborate with Synopsys and accomplish several enhancements in the PowerReplay. In this paper, we will share our experiences of applying those useful enhancements on our real projects.

Thank You to Our Sponsors

  • ARM Platinum Sponsor
  • GlobalFoundries Platinum Sponsor
  • Samsung Platinum Sponsor
  • TSMC Platinum Sponsor
  • AWS Gold Sponsor
  • aws Gold Sponsor
  • Google Gold Sponsor
  • 聯華電子 Gold Sponsor
  • Synopsys Corporate