When the semiconductor technology advances to nanometers, designers can integrate more functions into a very small die area than that with the old technology. However, the flip side of the new technology is the high power density, and this problem brings severe IR and heat dissipation issues. Therefore, designers have to be very careful when doing the IR signoff. In our company, we enhance the IR signoff quality by increasing patterns, i.e., increasing the IR signoff coverage. However, this requires high human efforts with this solution, since we have to run the IR tool for each pattern and check if there is any IR violation in each pattern one by one. To reduce the execution efforts, we collaborated with Synopsys to propose a novel solution by utilizing the PowerReplay to sequentially merge several patterns into a single one. With this solution, users only have to run the IR tool and do the IR signoff once. This solution can reduce many IR signoff efforts and the quality keeps the same with the original method.

There are many common mathematics operations in current AI chips for applications such as digital signal processing and neural network activation functions. By combination of different Synopsys floating point DesignWare IPs, we can easily design a very complex mathematics digital circuits with very high precision.  However, it will cause some design integration issues, e.g., how to decide effective bits of each cascaded DW IP. In this paper, we will discuss how to verify a POW10 design and find out the highest precision using VC Formal DPV, a C to RTL equivalence checking tool.

To make design become FPGA friendly, we will make some modification to our design.Hence, our RTL database for FPGA will easily have unexpected design issues such as multiple driver and black box issue which make integrators cannot generate the bit file smoothly. ProtoCompiler(UCPC) is not specialized Lint tool, so it cannot find out the design issue fast and clearly, it cause the iteration time for FPGA dramatically increase. VC-SG is a professional Lint tool which have the capability to fast and clearly find out the design issue, and export the report to integrator to review. Also, VC-SG is great customized so that integrator can add or remove Lint rules. This paper will show the critical and common design issues that FPGA integrators usually suffer and how we use VC-SG to point out these critical messages to review.

System-level simulation based on virtual prototyping enables hardware/software integration and system validation with real-world applications before actual hardware or silicon is available. However, the efforts needed to build the platform models and the bring-up time of end-to-end prototyping are still expensive, sometimes the extra efforts beyond the standard development flow may weigh against benefits. This paper discusses a mixed SystemC/SystemVerilog simulation approach for improving the functional verification productivity at the IP level and summarizes the problems and solutions that should be concerned when applying Synopsys PCIe virtual I/O solution for hardware/software co-verification and performance validation at the system level. A virtualized PCIe based SSD system has been implemented to demonstrate its simulation speed, timing accuracy, required implementation time for behavior/timing model, and the system-level virtual prototyping bring-up time.

In order to reduce the verification time of the IP in development, we integrate our IP, SRAM and the Synopsys's DRAM subsystem in a simple AMBA system on the Synopsys's HAPS platform. Using the Synopsys's Transactors to replace the house-keeping CPU position, prepare data and start the verification procedure.

Video 4K/8K application is getting popular but the high performance requirements on FPGA prototyping is challenging. In most cases, lower frame rate makes FPGA prototyping unable to turn on 4K/8K monitor. Furthermore, even users can turn on the monitor with low frame rate on FPGA prototype, it still cannot fulfill human minimum eyes resolutions requirement, which means extremely video lag introduces unpredictable effects for design qualification. In this presentation, we propose a solution with HAPS native IP called CAPIM for video data recording to overcome this issue. The recorded video can be used not only for replay with adjustable speed but also be compared with golden frame image from simulation.

Comparing to previous SNUG papers about Save and Restart which is applicable for SoC environment. In this submission, I mainly focus on applying this feature for our IP verification environment (UVM-based environment) and its effects to overall performance by reducing simulation time.

PCIe is a widely used high speed serial interface bus standard. And the control logics inside the link layer are the infrastructure of packet transmission. In this presentation, we would like to illustrate how we successfully adopted formal technology on PCIe's newest extension: CXL link layer retry (LLR) module. And also how signoff methodology and coverage metrics supported by VC Formal provided measurable progress for us to complete the signoff process on a control intensive design with strong confidence.

The investment into tackling AI Hardware Acceleration has grown at breakneck speeds, with many vendors starting 2nd, 3rd, or 4th generation designs. Due to the fierce competition and ever-growing application opportunities for AI, Machine Learning Algorithms, Compilers, and Architectures are evolving rapidly and branching into more specific use cases. This competitive environment opens opportunities for differentiation and system optimization.Architecture modelling is required to optimize the AI SoC design through system and IP configuration alternatives, modelling the specific AI Algorithms intended for specific use cases. In this tutorial we will discuss the available tools, models, and IP to accelerate the early analysis and optimization of AI SoC Architectures.

Meeting ASIL-D for complex ADAS applications in Automotive SoC industry is challenging. The occurrence of a fault in safety-critical logic must be detected and reported to the higher level system. ARC Safety Processors that have Dual-Core Lock Step implementation offers this capability. To verify the effectiveness of the safety mechanisms to detect and report the occurrence of any random hardware faults in a safety-critical logic, Z01X fault simulator is used. A quantitative measure of the diagnostic coverage can be achieved through a Fault Injection campaign. Faults are deliberately inserted in the safety-critical logic through a fault simulator like Z01X, faults detected by the safety mechanism are then reported. In this presentation, we discuss how the fault injection campaign was exercised through Z01X on an ASIL-D ARC processor with DCLS for all the failure modes identified. We also discuss the remedies adopted to address the challenges during the fault campaign.

"Increasing emulation efficiency for networking SoCs using virtual testers In this tutorial we will review the challenges for pre-silicon software development and system validation for complex networking SoCs. We will propose state-of-the-art virtualization technologies connecting Keysight network tester technologies with ZeBu emulation and share case studies of successful use of the technology. We will share how emulation resources can now be used more efficiently compared to traditional in-circuit emulation."

Unified Compile 2.0 (UC2) provides a common frontend and allows for easy migration amongst Synopsys tools from simulation to Prototyping. Standard flow compiler of Prototyping tools has a few limitations such as SV interface, SVA and XMR behaviors. Migrating from Standard flow compiler to UC2 can not only improve language support during compilation, but also resolve the mismatch between different front ends to boost the verification productivity.
Unified Debug is an extension of the Unified Compile, which provides the users the ability to provide debug information. As well as legacy SRS instrumentation, it allows users to use $dumpvars and SVA common seen in the RTL simulation to easily add instrumentation. Besides, Verdi integration and data expansion for GSV readback can maximize correlation and visibility.

Static verification catch chip-killer bugs without the need for testbenches, enabling a shift left, this includes Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC), Low Power (LP) crossings issues Synopsys’ SpyGlass Platform is the industry standard with the most in-depth analysis at the RTL design phase. And building on that industry leading technology we have delivered the next generation VC SpyGlass Platform to customers. This platform offers key innovative technologies like Machine Learning based Root Cause Analysis for lower noise and faster debug, Hierarchical verification using Signoff Abstract Model(SAM) delivering 10x increase in capacity and performance with no loss of QoR, Formal-enabled lint to reduce noise in structural analysis, netlist level CDC signoff to catch issues in logic added during implementation.

As automotive ethernet switch designs include more features and require more software control, there is need to deploy virtual prototypes to “Shift Left” (start software development earlier). In this particular use case, we utilized Virtualizer and the virtualized interfaces to create an end-to-end virtual prototype for automotive ethernet switch. This virtual prototype allows software engineers to develop and test their software without RTL.

Next-generation SoCs with advanced graphics, computing and artificial intelligence capabilities are posing unforeseen challenges in verification. UPF (Unified Power Format) and design development goes hand in hand, but schedules may vary. It is difficult to verify the accuracy and correctness of the UPF without the design being available. There are many UPF issues which can be caught independent of the design with the new design independent UPF checker. Designers and verification engineers using static verification technologies for low power often see many violations in the initial stages. Efficient debugging and root-causing real issues is a big challenge when violation counts are huge. This paper will talk about the current application of deterministic and machine learning-based techniques to automatically identify the accurate root-causes for a related group of violations. The paper showcases these methodologies along with the results that can be achieved with a “shift-left” in overall low power static verification signoff.

In the context of parametric designs, the number of DUT configurations increases the complexity of the verification task, especially in the formal verification domain. Qualifying a formal verification environment targeting multiple configurations of the same parametric design can easily become overwhelming from the point of view of the execution time. This paper presents a technique to reduce the effort spent into qualifying a given configuration, taking advantage of the information collected from other configurations. This technique produces a “smart” subset of assertions for Certitude to run with higher priority, because their probability to detect a given injected fault is higher, resulting in a sharp reduction in the execution time. This paper describes the case study onto which the technique was experimented and the results in terms of saved execution time. The outcome of this paper has become a feature of Certitude starting from version 2019.06.

Designs have to deploy techniques to detect Single-Event Upset (SEU) and mitigate its impacts, especially for security and safety applications where such errors may have grave consequences. Formal method is well-suited for verifying such designs if SEU effect could be described in formal verification framework. For most of these designs, the effect of SEU could be abstracted as a random state bit flipped. This paper presents a novel state element modeling scheme to allow designs being verified for SEU effect with formal property verification app. A twice fast reference clock is used for controlling the timing of SEU event. The scheme has been applied to the verification of a design for assessing its resilience to SEU, in addition to validating implementation of SEU mitigation techniques on its state machine and critical control signals. The scheme can also be extended to Multiple Bit Upset (MBU) situation seamlessly.

In shift-left, SoC validation is a critical stage in large designs where different IPs of varying complexity are integrated together in a single design. So accelerating the debug turnaround times for failures in both design and testbench becomes important for faster product development. When tests exercising the same intent are run at both IP and SoC levels, most of the times a huge amount of time is spent in debugging failures which result from IP configuration issues. If the IP itself has a large number of configuration registers used for various functionalities, deciphering each incorrect IP configuration register programming is difficult if the IP functionality itself is highly complex. When the IP contains a block doing Virtual Address (VA) to Physical Address (PA) translations using multiple complex page walks and memory range checks, it is useful to create checks at each step of the translation process to pinpoint the root cause of translation mismatches and/or read/write cycle invalidations quickly. This paper presents an effort to accelerate the debug turnaround times at SoC by considering IP as a golden reference. We achieve this by developing post-simulation checkers using the simulation waveform database which help catch all IP configuration and VA to PA translation issues efficiently and thus save hours of debugging time. We present examples of using our checkers for a graphics IP integrated into an SoC.

With the expansion in hardware portfolio purpose-built for AI and new software offerings, there are new opportunities for AI in the cloud, the data center or at the edge. At the edge, not only performance is important, but customers also care about power, size and increasingly, latency. In this paper and presentation we outline an approach to create a performance modeling methodology for evaluating Use Case Key Performance Indicators (KPIs) on the next-generation AI Inference accelerators for media and computer vision applications. The paper will elaborate on the methodology to integrate and build cycle approximate representative SoC performance models, the challenges, and some results.