Dynamic voltage drops affect the CPU performance significantly and their waveforms measured inside the SoC is hard to be taken. In order to confirm the proposed methodology of chip-package-board co-simulation is reliable to predict the voltage drop inside the SoC, the simulated results were compared with the measured maximum voltage drops on both the PCB and the package. Good correlations indicated that the error of maximum voltage drops were less than or equal to 15.3 mV if the measured time frame is 10 msec based on 1 V power supply. When the measured time frame was shorten in 20 μsec, the error was improved to less than or equal to 0.3 mV. The following co-simulations found the acceptable configuration of decoupling capacitors (decap) for major power nets passing the limitation of maximum 8% voltage drop inside the SoC. At the same time, the maximum executing speed of dual big-core CPU was promoted from 1.4 to 1.6 GHz without any layout modification of both PCB and package. Selection of large capacitance decap in the package is recommended for CPU power nets consumed with high current. Also, the merged power nets of big-core and little-core CPUs in the PCB is not recommended unless they star the maximum power asynchronously.

In cell based design flow, timing closure which involves STD cell replacement is inevitable to make sure the design passes back-end signoff checks across various PVT conditions. The iterations usually take from hours to days and greatly increase turn around time. In this paper, a delay sensitivity ranking method is proposed to filter out STD cells whose delays are sensitive to PVT variations based on timing library database characterized by SiliconSmart. By marking these sensitive cells as dont_use, the timing closure iterations can be reduced thus increases efficiency of overall design flow.

The purpose of this article is to show you how to improve your design quality and accelerate circuit design by using Custom Compiler Schematic Entry (CCSE) in the TSMC 0.18 BCD process. Nowadays, RD Engineers are facing more and more complicated challenges. CCSE is an unique tool which is integrates with LakerOA, HSPICE, Finesim and Waveform tools to closely work together. It is more convenient for RD Engineers to design, debug, and communicate with Layout tool.

Share the case study of FineSim SPICE performance improvement on post-simulation.

CCLE adoption experience sharing.
- Faraday Introduction
- Why Faraday Adopt Custom Compiler LE in FinFET
- Layout Environment Customization/Migration Overview
- Custom Compiler Benefit Features Sharing

By Laker L3+ feature to help layout user improve productivity in power design layout.
Also easy define criterial rule for window DRC check and reduce layout communicate with RnD by writing some constraint in design.
For digital block routing, also provide solution to placement and routing STD cell in Laker environment. Also help some small digital block quick routing.
Laker L3+ not only improve layout productivity and also robust our design.

High capacity usage of Memories on a chip, lower supply voltages and other challenges associated with the technology scaling, increases the probability of failure in Memories on silicon. This pushes the need for enhanced statistical analysis with a large Sigma qualification (>6sigma) in Memories to ensure design robustness and subsequently reduce the failure rates. In this work, we discuss two aspects of how we simulate to assess variability. The first part involves running Monte Carlo simulations on bitcells, where the target sigma-qualification is as high as 6.0 or even larger. We present results of both HSPICE LSMC (> 1B samples) and HSMC that is used to estimate the yield. Using HSMC significantly improves the turnaround for these simulations. Second part of our work focuses on running Monte Carlo on full memory instance using Sigma Amplification. CustomSim is the tool of choice for simulations over full Memory instance because of its superior throughput combined with good accuracy. We will present how Sigma Amplification helps us to uncover worst-case failing points and fine tune our design to increase design robustness.

The performance of deep submicron designs which are developed with the latest technologies is affected by various parametric and statistical process variation and increasingly impacts the robustness of various circuit types. In this paper we discuss many statistical concepts that are used in variability analysis and can be used to process data generated in Monte Carlo Analysis. Also, we introduce HSPICE High Sigma Monte Carlo, and perform a comparative analysis with conventional Monte Carlo on the stability and performance of several types of sensitive circuits. Thus, detailed analysis is performed that show the efficiency of High Sigma Monte Carlo in producing results in shorter runtime and using less compute resources, allowing efficient MC analysis of more vulnerable circuits.

The functional verification of a mixed-signal IP continues to evolve where more focus is on quicker execution with high quality. Shift left methodology (top-down design) has been followed in many stages of execution, one of which is functional simulation with SystemVerilog based behavioral models (BMOD) representing the analog blocks within an IP. Even though not all analog features can be modelled in BMODs, the fast runtime makes it a viable alternative for functional verification of the IP design. The purpose of this submission is to present a methodology to reuse the simulation cycles from the above mentioned practice to automatically generate testbenches for feature level validation of these analog blocks in both schematic level and BMOD level. The reuse of testbenches helps consistency in validation across cross-functional teams working on different stages of execution like analog circuit design, BMOD development and IP level functional verification. This allows for quicker turnaround from spec change to modelling and vice-versa while preserving the accurate behavior in SoC level sims without running the full simulation.

As critical dimension of SRAM scales down continuously, the impact of process variations becomes more significant and further pushes the design margin. Therefore, in order to have a robust bitcell design, it is vital to have a reliable simulation tool, which can deal with high-sigma (up to 6.5 sigma) Monte Carlo simulations within acceptable runtime. In this study, Synopsys HSPICE-AVA high-sigma Monte Carlo (HSMC) tool was used to evaluate two test cases. The first test case was high voltage (~0.8V) and near subthreshold voltage (~0.5V) simulations for worst case SRAM read current. The second test case evaluated was for SRAM write time. Two fail modes with different corner sensitivities were tested. Clear transition from one fail mode to the other was observed when bias voltage was pulled down. Results showed that the Synopsys high-sigma Monte Carlo tool showed comparable results (~0.01% delta) to typical Monte Carlo simulations with run time reduction of about 2 orders of magnitude. The tool successfully captured the non-Gaussian distribution for advanced node and was also able to find the right fail mode.

This presentation will provide a front-to-back overview of how Synopsys Custom Platform can be used to design for reliability. Areas covered will include static and dynamic circuit checks, aging, electromigration, Monte Carlo analysis and custom fault.

Synopsys TestMAX CustomFault is a breakthrough new product that enables full-chip analog fault simulation. With its industry-leading CustomSim FastSPICE technology and Adaptive Weighted Random Sampling, TestMAX CustomFault delivers orders-of-magnitude performance improvement for functional safety and test coverage analysis. The presentation brings the concept of analog fault simulation to engage with the incoming more and more design application on automotive.

To address the more and more complexity of designs and processes, the capabilities of simulators are getting more and more important including the performance, analysis methodology and flow. Synopsys keep investing the AMS simulation products to facilitate the need of modern advanced designs. Through the presentation, user can get the most updates of the new features and enhancements of HSPICE, FineSim and CustomSim and know how they will benefit to the daily circuit simulation works.

Custom layout creation faces many challenges in advanced FinFET processes. Custom Compiler develops a correct-by-construction design flow for designers to complete layout and closer collaboration by visualized layout assistants. It improves better layout productivity while keeping controllable quality. There are many assistants to reduce user effort and to avoid human mistake, For example, Expand Schematic for top down floorplan, place pins, preset, SED, ICV-live, GCR, Net Base Check…. Custom layout creation faces many challenges in advanced FinFET processes. Custom Compiler develops a correct-by-construction design flow for designers to complete layout and closer collaboration by visualized layout assistants. It improves better layout productivity while keeping controllable quality. There are many assistants to reduce user effort and to avoid human mistake, For example, Expand Schematic for top down floorplan, place pins, preset, SED, ICV-live, GCR, Net Base Check….