Synopsys Users Group Taiwan 2020

新思科技 (Synopsys) 的 SNUG Taiwan (Synopsys Users Group - Taiwan) 技術研討會邁入第二十周年,今年活動將探討當前5G、物聯網、車用電子及人工智慧(AI)等科技發展趨勢,及其所涉及的晶片設計與相關軟硬體整合的新技術。為因應COVID-19防疫措施,今年SNUG Taiwan活動採線上研討會方式進行,誠摯邀請 您一同參加「SNUG Taiwan 2020」線上研討會,掌握產業新契機。
請點選 Sign up/Login 完成預先線上報名及帳號啟用手續,即能在研討會上線期間(7/1~7/15) ,點閱影片觀看。

抽獎禮:完成報名並有效完成post-event問卷,就有機會參加抽獎,獎品包括Garmin VENU AMOLED GPS 智慧腕錶乙只,以及Dyson Pure Cool Me purifier fan 空氣清淨風扇乙台。

For 20 years, SNUG Taiwan (Synopsys Users Group - Taiwan) has become one of the largest technical conferences in Taiwan’s semiconductor industry community. Coping with the COVID-19 pandemic measures, SNUG Taiwan 2020 is going online and exploring trends and technology developments for 5G, IoT, Automotive electronics, and AI, etc. The SNUG Taiwan On Demand features Synopsys Keynote from Chairman & co-CEO Aart de Geus and over 40 technical sessions including user papers and presentations, and Synopsys tutorial presentation recordings.
Please click Sign up/Login to complete the online registration and account activation. The pre-recorded presentation videos will be live from July 1 to July 15.
The giveaways and lucky draw incentives for SNUG Taiwan 2020 only apply to event participants in Taiwan. These prizes won’t be sent to regions or countries outside Taiwan.

備註 1:參加獎數量有限,送完為止。
備註 2:抽獎活動將線下進行,主辦單位將另行通知獲獎者。
備註 3:活動僅限於台灣地區舉辦,獎品恕無法寄送至非台灣地區。
備註 4:台灣新思科技對活動規則擁有最終解釋權。
All rights reserved to Synopsys for agenda and rules change.

The Tools of Vitality

Aart de Geus
Chairman and co-CEO, Synopsys

Whether it’s managing the threat of a global pandemic or the pursuit of better-faster-cheaper semiconductors, tomorrow’s innovation success stories will be defined by how they overcome systemic complexity and dominate the exponential curve.
Dr. de Geus will examine some of the trends, opportunities, and emerging toolkits that will enable industry leaders to optimize the future of innovation, collaboration and smart everything.

After COVID-19

David Lin
Corporate Senior VP of Synopsys Asia Pacific Region

In this talk, David will summary the impact of COVID-19 brought to semiconductor industry in 2020 and beyond. He will address the opportunities & challenges and share how Synopsys is working with world leaders through invented technologies.

Technical Committee Paper Award

Best Paper Award
Early Software Development and End-to-end System Validation using Virtual Prototyping and UVM Testbench
James Lai
System-level simulation based on virtual prototyping enables hardware/software integration and system validation with real-world applications before actual hardware or silicon is available. However, the efforts needed to build the platform models and the bring-up time of end-to-end prototyping are still expensive, sometimes the extra efforts beyond the standard development flow may weigh against benefits. This paper discusses a mixed SystemC/SystemVerilog simulation approach for improving the functional verification productivity at the IP level and summarizes the problems and solutions that should be concerned when applying Synopsys PCIe virtual I/O solution for hardware/software co-verification and performance validation at the system level. A virtualized PCIe based SSD system has been implemented to demonstrate its simulation speed, timing accuracy, required implementation time for behavior/timing model, and the system-level virtual prototyping bring-up time.
Best Paper Award
6/7nm Design Routability Analysis and Improvements with IC Compiler II
Yu-Wei Tseng
In this presentation, we shall discuss methodologies which can be used by designers for analyzing and/or improving the routability of physical layout designs (including standard cells). These methodologies include GR (global routing) modeling, standard cell pin access checking, pattern matching based routability improvements, and routability analysis for feedthrough nets.
Outstanding Paper
Sequential Waveform Merging Solution for Minimizing IR Signoff Efforts
Yu-Shuan Liao
When the semiconductor technology advances to nanometers, designers can integrate more functions into a very small die area than that with the old technology. However, the flip side of the new technology is the high power density, and this problem brings severe IR and heat dissipation issues. Therefore, designers have to be very careful when doing the IR signoff. In our company, we enhance the IR signoff quality by increasing patterns, i.e., increasing the IR signoff coverage. However, this requires high human efforts with this solution, since we have to run the IR tool for each pattern and check if there is any IR violation in each pattern one by one. To reduce the execution efforts, we collaborated with Synopsys to propose a novel solution by utilizing the PowerReplay to sequentially merge several patterns into a single one. With this solution, users only have to run the IR tool and do the IR signoff once. This solution can reduce many IR signoff efforts and the quality keeps the same with the original method.
Outstanding Paper
How to efficiently improve FPGA quality with VC-SpyGlass-Lint/CDC ?
Ryan Yang
To make design become FPGA friendly, we will make some modification to our design.Hence, our RTL database for FPGA will easily have unexpected design issues such as multiple driver and black box issue which make integrators cannot generate the bit file smoothly. ProtoCompiler(UCPC) is not specialized Lint tool, so it cannot find out the design issue fast and clearly, it cause the iteration time for FPGA dramatically increase. VC-SG is a professional Lint tool which have the capability to fast and clearly find out the design issue, and export the report to integrator to review. Also, VC-SG is great customized so that integrator can add or remove Lint rules. This paper will show the critical and common design issues that FPGA integrators usually suffer and how we use VC-SG to point out these critical messages to review.