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Join us at SNUG Taiwan 2022. Pre-registration is required.

SNUG TW 2022 – A Virtual Experience  


鑑於近期COVID-19本土確診案例尚未明顯趨緩,考量與會貴賓健康安全及配合政府強化防疫政策,SNUG Taiwan 2022 仍維持線上形式舉辦。誠摯邀請您一同參加SNUG Taiwan 2022線上研討會,瞭解當前IC設計及半導體產業最先進的技術和研發趨勢,激發創新思維以因應設計和驗證面臨的嚴峻挑戰,進而掌握產業新契機。


請點選 Sign up/Login 完成預先線上報名及帳號啟用手續,即能在研討會活動期間(7/11~7/25),隨選影片點閱觀看。活動期間完成觀看4支影片及對應session 問卷,並完成post-event 問卷,除了可以下載會議資料外,並可參與抽獎。獎品包括iPhone 13(1名)、Garmin Venu 2 Plus智慧手錶(1名)、Nespresso Lattissima One膠囊咖啡機(1名)、HyperX Cloud Alpha Wireless無線耳機(1名)及新台幣500元的foodpanda即享券(500名)等多項好禮。


SNUG Taiwan所有內容將於活動結束後90天上傳至新思科技技術支援服務平台SolvNetPlus


The health and safety of the SNUG ecosystem – including users, partners and our employees – are a top priority of Synopsys. 

Due to recent COVID-19 surge that have raised concerns among attendees and presenters about assembling in a large group, SNUG Taiwan Operation Team had made a decision to host SNUG Taiwan on-line. You are sincerely invited to participate in the SNUG Taiwan 2022 online seminar to learn about the most advanced technology and R&D trends of current IC design and semiconductor industry.


Please click Sign up/Login to complete the online registration and account activation. The pre-recorded presentation videos will be available on-demand starting from July 11. All content will be moved to SolvNetPlus after 90 days.


備註:

  • 禮品以實物為準,如遇不可抗力因素,則以等值獎品替代之。
  • 抽獎活動將線下進行,主辦單位將另行通知獲獎者,並於活動首頁公告得獎名單。
  • 活動僅限於台灣地區舉辦,獎品恕無法寄送至非台灣地區。
  • 台灣新思科技保留修改本活動規則之權利,並對活動規則擁有最終解釋權。

The incentives for SNUG Taiwan 2022 only apply to event participants residence in Taiwan.

All rights reserved to Synopsys for agenda and gamification rules change.

Welcome to SNUG Taiwan

半導體技術瞬息萬變,一年一度的SNUG Taiwan為台灣半導體設計與製造業界規模最大的技術會議之一,展示來自全球晶片設計領域最先進的創新技術。同時持續促進新思科技的用戶和技術專家之間的聯繫,以分享電子設計和驗證挑戰的最佳實踐。

今年SNUG Taiwan主題演講,將由新思科技董事長暨共同執行長Dr. Aart de Geus及矽晶實現事業部(Silicon Realization Group)總經理Shankar Krishnamoorthy,分享新思科技在AI、EDA Cloud等半導體創新技的策略佈局。另外邀請客戶代表針對AI、車用電子以及3DIC等技術發表設計研究心得;並集結來自SNUG SV 2022的精彩內容,除了新思科技的產品應用教程(tutorial)外,還包括AMD、Arm、Intel、NVIDIA、Samsung、Sony等全球夥伴,就前述主題分享的技術專題。


Our world of technology is changing rapidly and SNUG Taiwan strives to demonstrate the state-of-the-art innovations from the chip design community around the globe. It also continues to foster the link between Synopsys’ tool users and technical experts so they can share best practices for electronic design and verification challenges.


This year, SNUG Taiwan features insightful keynotes from Aart de Geus, Synopsys Chairman & co-CEO and Shankar Krishnamoorthy, GM of Silicon Realization Group at Synopsys and diverse technical tracks driven by innovative user content, and leading-edge Synopsys tutorials that remains committed to delivering an exciting conference. We hope you’ll enjoy viewing them.


Robert Li

Synopsys Sales VP and Chairman/President of Synopsys Taiwan


備註:新思科技保留議程調整權。

NOTE: The agenda is subject to change without prior notice.

Program Overview & Paper Summary

CW Ko
DGM of MediaTek Inc.

SNUG Taiwan 2022 Committee Chair


Thanks the members of the Technical Committee who volunteer their time and expertise to support SNUG's technical quality and deliver the benefit of their perspective to the users of Synopsys tools and technology. 


SNUG Taiwan 2022 Committee Members:

YC Chang, Realtek
Jerry Chen, Himax
WL Hsu, Nuvoton
Albert Li, CVT Semi
Daniel Ping, Novatek
Mathew Tsai, GUC
Fuchu Wen, Phison
KC Wu, Faraday
Adan Wu, M31

*Alphabetically listed by last name.

Catalyze the Impossible

Aart de Geus
Chairman and co-CEO, Synopsys


For decades our industry has focused on achieving improvements to semiconductor speed and area – and we have accomplished that. The superior performance of today’s semiconductors, multiplied by the capabilities of artificial intelligence, enable us to collect and analyze data such that we can now anticipate potential problems, in domains such as human health and climate. Synopsys Founder and co-CEO Aart de Geus kicks off SNUG with a look at how decades of semiconductor advancement enable unleashing the potential of semiconductors, computing, data analysis and AI in ways that hold the potential of transforming human existence.

From Atoms to Systems, EDA Innovation in the SysMoore Era

Shankar Krishnamoorthy
GM of Silicon Realization Group at Synopsys


Shankar Krishnamoorthy, GM of Silicon Realization Group at Synopsys will discuss macrotrends in innovation that leverage both software and chips to create world-changing products. Referred to as the SysMoore era, Shankar will describe the forces that got us to this new model of innovation and discuss the substantial challenges that must be addressed. He will then provide some examples of the investments Synopsys is making to unlock the vast innovation potential before us.

Technical Committee Paper Award

Best Paper
(中文簡報) Achieving the Best PPA on Imagination GPU with Fusion Complier
Kuo-Liang Cheng, Cloud Tsai
Realtek
PPAT Closure on Imagination GPU Using Fusion Complier
Best Paper
(中文簡報) HSIO DFT: next-gen. DFT architecture with re-definition of existing design
Anti Tseng, Pei-An Ho
MediaTek Inc.
This HSIO DFT concept was proposed around 2 years ago, but not really implemented into real chip because of limited IO bandwidth and immature ECO-system including tool & ATE instrument. By close co-work among Synopsys and AdvanTest, this concept has become much more applicable in late 2021. MediaTek will become pioneer to implement HSIO DFT in two consecutive chips as part of technology roadmap. This submission will cover how we assess this technology and latest experiences earned which could benefit other SNUG attendees.
Best Paper
(中文簡報) Machine Learning for Improving PowerReplay Accuracy
Chia-Cheng Wu, Yu-Shuan Liao, Kai-Hsin Hsu, Shang-Wei Tu, Grant Pan, Martar Shih, Jack Yen, Marty Huang
MediaTek Inc., Synopsys
Correct and realistic behaviors of power critical points in a digital design waveform can guarantee the accuracy of the power estimation. The power critical points could be clock-gating enable pins or SRAM input pins. Since these points are not Primary Inputs (PIs), registers, and the output pins of macros, they cannot be mapped in the standard flow of the PowerReplay. Therefore, we have collaborated with the Synopsys PowerReplay team to create a VCApp “via_map_map_cg” to map those critical points of a netlist to the corresponding RTL signals in the waveform. However, this VCApp is not capable of mapping some complicated points under multiple Verilog “generate” block layers. In this paper, we collaborate with the PowerReplay team to propose a new Machine Learning (ML) technique to improve the mapping quality of the VCApp. With the trained model, the proposed technique can improve the mapping quality for several real designs.
Best Paper
(中文簡報) Using ML-Delay in Advanced Process Node for Better PPA and Runtime with IC Compiler II
HsinJu Tsai, TK Tsai
MediaTek Inc.
Current IC design is confronted with huge architecture or design expansion. Compared with mainstream and mature process nodes, different sets of design rules and complex sign-off restrictions. Thus, the pre-route to post-route correlation is more challenge in the advance process nodes. Therefore, there is a need of developing new methodologies for the purpose of getting better PPA and improving physical design flow runtime. In this presentation, we shall discuss methodologies which can be used by ML-delay (machine learning) flow for training the model to correlation between each PNR stage and doing ML prediction for better PPA. These methodologies classify by different scope include block level and project level which can support difference design structure and more accurate prediction to training model.
Outstanding Paper
(中文簡報) Insight of PowerReplay
Shang-Wei Tu, Marty Huang
MediaTek Inc., Synopsys
Recently, the power consumption of chips becomes a very hot topic for mobile devices, especially for smartphones. The high power consumption brings many troubles both before and after the tapeout. Before the tapeout, the high power makes worse IR, system PI, and thermal problems. After the tapeout, it also impacts the user experience by degrading the performance (due to thermal throttling) and shortening the device operation time. Hence, accuactely and efficiently predicting the power before the chip tapeout for the successive analysis and optimization becomes the key in the design flow. We adopt the PowerReplay in our power analysis flow. However, there are many factors could impact the accuracy of the result of the PowerReplay. In this paper, we share our experiences of those factors and possible solutions. With those factors properly solved, we can get average 98% accuracy of the power analysis result comparing to the post-layout simulation waveform.

Thank You to Our Sponsors

  • arm Platinum Sponsor
  • GlobalFoundries Platinum Sponsor
  • MicrosoftAzure Platinum Sponsor
  • Samsung Platinum Sponsor
  • TSMC Platinum Sponsor
  • AWS Gold Sponsor
  • Ansys Gold Sponsor
  • Intel Foundry Service Gold Sponsor
  • UMC Gold Sponsor